[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the following cases are now successfully detected:

* read-after-write: instruction is issued but stalls,
   other instruction issue is NOT stalled (making
   the core "superscalar")
* write-after-write: instruction is NOT issued, but is
   captured and acknowledged back to the Issuer.
   attempts to issue continue and will succeed when
   the WaW hazard clears
* read-and-write-by-same-instruction: this case is
   covered by DELAYING write-hazard setting by one
   clock cycle, such that the RaW hazard check does
   NOT include the instruction currently being issued

potential problems to monitor:

* if the write-hazard bitvector setting is delayed, and
   the write to its SR Latch is also delayed, then two
   instructions issued one clock cycle apart might not
   properly detect read-after-write hazards.

   right now this is undetectable because the FSM
   of TestIssuer cannot issue instructions that fast
   (1 every 4-5 cycles)

* LD/ST instructions must not be acknowledged
   unless the opportunity for an exception has passed

* likewise branch and trap (anything that changes PC)

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