[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Nov 19 13:05:35 GMT 2021


--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #21)
> I was thinking about the "core stopped" signal for DMI.
> I think it could be generated by the AND of all the "o_ready" signals of the
> reservation stations. When all reservation stations are ready, it means they
> are not processing any instructions, and the core is stopped.

ah no, it has to also include the DMI state of the user request.
as in: yes, you are right: stopped can be generated that way, but
ONLY when requested to do so.

> Another way would be to maintain a (small) counter of issued instructions,
> and another for retired instructions. When they match, there is no
> instruction in flight, and the core is stopped.

there is already an fu busy signal per FU, a counter is not needed.
an OR of all FU Busy signals is already how the FSM "busy" is generated
right now.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list