[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the integration of bitvectors went perfectly right up to the moment when
a combinatorial loop was detected.  the loop is as follows:

* bitvector regfiles were set to a combinatorial variant on operand
  forwarding.
* this so that set/clear of writes could be detected immediately by
  the read hazard, in the *current* cycle
* this so that issue could be held until the instruction was ready

unfortunately the actual setting/clearing is gated by FU issue/busy
which is also combinatorial which results in the read of the bitvector
being dependent on setting/clearing which then gates issue and hence
there's a loop.

the solution - which occurred to me just now - is this:

* make the bitvector regfiles a sync (one-clock delay)
* request the read of the bitvector at issue time (bear in mind
  it will arrive 1 clock late but that's ok because...)
* once issue is set, only on the *next* clock will the read-requests
  be set, at which point...
* the bitvector hazard read will also arrive and...
* if any bit is set, the read-requests can be gated out (prevented)

the irony is that this is *exactly* and i do mean exactly the job of
a FU-Regs Dependency Matrix

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