[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #21 from Cesar Strauss <cestrauss at gmail.com> ---
I was thinking about the "core stopped" signal for DMI.

I think it could be generated by the AND of all the "o_ready" signals of the
reservation stations. When all reservation stations are ready, it means they
are not processing any instructions, and the core is stopped.

Another way would be to maintain a (small) counter of issued instructions, and
another for retired instructions. When they match, there is no instruction in
flight, and the core is stopped.

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