[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Nov 17 18:13:44 GMT 2021


--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 7492a3533c61a6999d36df687c8d5e6e3603b0d6 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Nov 17 18:01:27 2021 +0000

    reading of regfile bitvector added, which activates on a per-FU basis
    at the regfile read port

    this is somewhat complete overkill because strictly speaking the
    read should be done at issue time.  fortunately, merging of lots of ORs
    results in the exact same thing, just distributed

    horribly inefficient though

to make use of pre-existing for-loops and data structures,
at each (distributed) point can raise its flag, "is the main decoder requesting
that this register be read"

actually what is needed is: back in the connect_instruction() function
all available decode_regfile_read() functions are called there and then,
only the once, for each register.

looking at decode_regfile_read() there should, strictly speaking, be 17
separate bitvector requests/merges. at present there are *30* because
MUL requests RA, ALU requests RA, etc. etc.

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