[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cesar i added a FetchOutput data structure, for fetch pipeline ospec():

https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=f1c63229cdf94d9fbca54086ff13d6a149245814

class FetchOutput:
    def __init__(self): #, svp64_en):
        self.state = CoreState("core_fetched")
        self.raw_insn_i = Signal(32) # one raw instruction
        self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE

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