[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
the write protection hazard vector is now in place but is not in
use.  there is further work needed to cover the situation where
Data.ok is not set by the ALU but wrflags was set.  this is
reasonably straightforward to do.

after that, the bitvector read is ready to try out, and that can
be done with TestIssuer by using a DIV and an ADD instruction.
DIV will take many more cycles than the FSM so is perfect to try.

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