[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Nov 11 14:37:25 GMT 2021


--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

i am slowly morphing core so it can have regfile hazard vectors
(which you won't need to start with as long as running test
instructions that avoid hazards)


this puts the requested port names into a pair of dictionaries.
i can then, for the "Hazards" regfiles, request the exact same
names, which will make it much easier in core.py to create a
matching "bit-setter" / "bit-clearer" system.

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