[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=7036fbf292ed8a5bc8393c3c95e15a28870ee325

i now have a suite of PriorityPickers at the front of Core issue.

this means that only one FU will ever get picked (even if there
are multiple ReservationStations).

this can actually be tested even with TestIssuer by issuing a DIV
instruction followed by (a few) add instructions.  the DIV will
still be running (64+ cycles) whilst the ADD gets round to being
loaded and issued.

of course if the DIV instruction tries to use the same registers
as the ADD it will get the wrong answer, but it will be a way
to test whether overlapping instructions can work at all.

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