[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #9)
> so instead of lut = Signal(4) it would be lut = Signal(8)
> and the assignment would either come from self.fields.FormTTI.TTI
> or just directly accessing the instruction (bearing in mind
> Power ISA spec madness)

Note that the form I added is called TI (for TernaryI) and the immediate field
is called TII (for TernaryI Immediate).

(In reply to Luke Kenneth Casson Leighton from comment #3)
> OP_TERNARY not OP_TERNARYI

I decided to leave the internal op set to OP_TERNARYI since the ALU will need
to distinguish ternary/ternaryi to correctly read either RC or the TII field --
also they will have a different number of registers, which might cause problems
with the instruction issue logic if they are assigned the same internal op.

(In reply to Luke Kenneth Casson Leighton from comment #10)
> so, the CSV can have RT now as in3 (replacing CONST_TII which should
> be removed from In3Sel)

Done:
https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=782d622d51388374db95c98b8a7ee7cfa8c3e30b

I also fixed sv_analysis to properly handle it

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