[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #11)
> (In reply to Luke Kenneth Casson Leighton from comment #9)
> > so instead of lut = Signal(4) it would be lut = Signal(8)
> > and the assignment would either come from self.fields.FormTTI.TTI
> > or just directly accessing the instruction (bearing in mind
> > Power ISA spec madness)
> 
> Note that the form I added is called TI (for TernaryI) and the immediate
> field is called TII (for TernaryI Immediate).

the convention, created by the microwatt team, and followed in all 75
operations, is to use the same microcode op for both immediate and
nonimmediate.
this is achieved by placing the immediate into the data lanes of the registers
whereupon the Function Unit knows nothing at all about immediates and 
consequently a designation and naming convention based on immediates
is completely inappropriate and misleading.


> (In reply to Luke Kenneth Casson Leighton from comment #3)
> > OP_TERNARY not OP_TERNARYI
> 
> I decided to leave the internal op set to OP_TERNARYI since the ALU will
> need to distinguish ternary/ternaryi to correctly read either RC or the TII
> field

this is normally handled by the Muxers built in to MultiCompUnit
which is specifically designed to recognise a Record field "imm_data"
which places the contents of that data into the 2nd src operand
(nominally designated RB).

i explained the logic in earlier commwnts:
in this case 4 operands is too much therefore we are not
going to add it (or use imm_data, because the RB CompUnit lane is needed
for one of the 3 register inputs)

breaking the convention however is unwise so please rename it so
that a 2-operand non-immediate variant can be done later

> (In reply to Luke Kenneth Casson Leighton from comment #10)
> > so, the CSV can have RT now as in3 (replacing CONST_TII which should
> > be removed from In3Sel)
> 
> Done:
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;
> h=782d622d51388374db95c98b8a7ee7cfa8c3e30b
> 
> I also fixed sv_analysis to properly handle it

brilliant. that should be enough to move on to creating the pipeline
and its data structures, regspecs, and pipe_data.py

there aren't any 3-input pipelines (no FMAC yet) but the closest
to copy as a starting point is likely to be shiftrot.

there is no need to add a ti_imm field to the record because as already
explained the TI field can be extracted manually.  this saves wires.

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