[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)
> maybe we should have:
> input A: RA
> input B: RB
> input C: RT

these are the options in power_enums.py:

@unique
class In1Sel(Enum):
    RA = 1
    RS = 4  # for some ALU/Logical operations

@unique
class In2Sel(Enum):
    RB = 1
    RS = 13  # for shiftrot (M-Form)

@unique
class In3Sel(Enum):
    RS = 1
    RB = 2  # for shiftrot (M-Form)
    RC = 5  # for SVP64 bit-reverse LD/ST

therefore:
* input 1: RA
* input 2: RB
* input 3: has to be done as a special-coded case (RT) similar to
           how LD/ST-with-update is done (RA)

like this:

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_decoder2.py;h=edf2893b3dec4749822db7d926efb4eaa0eea9b2;hb=HEAD#l469

 469         if hasattr(op, "upd"):
 470             # update mode LD/ST uses read-reg A also as an output
 471             with m.If(op.upd == LDSTMode.update):
 472                 comb += self.reg_out.data.eq(self.dec.RA)
 473                 comb += self.reg_out.ok.eq(1)

therefore in class DecodeC, it would be:

   with m.If(op.internal_op == MicrOp.OP_TERNARY):
     comb += self.reg.data.eq(self.dec.RT)
     comb += self.reg.ok.eq(1)

or... yyeah, add RT as one of the sources for DecodeC.
i'll do that now.

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