[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)
> maybe we should have:
> input A: RA
> input B: RB
> input C: RT
> input D: imm
> output: RT
> 
> since that way we won't need to shift RA and RB over into inputs B and C
> saving a few gates.
> 
> input D can just be implicit in the CSV (the ALU extracts the immediate
> rather than using the decoder to do that) until we implement 4-in 1-out
> instructions.
> 
> How does that sound?

Satellite decoders can pick up immediate operands on their own, or
even decode the fields inside the instruction, let me
find an example...  ok here's a simple one (a single bit):

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/main_stage.py;h=253664032fc16a1401665416a70e33688c6caa65;hb=04c4144f0d962bb181c69de4ce5a998077314e24#l97

  97             with m.Case(MicrOp.OP_CNTZ):
  98                 XO = self.fields.FormX.XO[0:-1]
  99                 count_right = Signal(reset_less=True)
 100                 comb += count_right.eq(XO[-1])

ah, and this one, actually does further decode of the *register* fields:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/cr/main_stage.py;h=5f1edc7adb6fed02a2fc08b2a5ff0891905eabe9;hb=04c4144f0d962bb181c69de4ce5a998077314e24#l74

  45         xl_fields = self.fields.FormXL
  ...
  ...
  74                 # Get the bit selector fields from the
  75                 # instruction. This operation takes in the little CR
  76                 # bitfields, so these fields need to get truncated to
  77                 # the least significant 2 bits
  78                 BT = xl_fields.BT
  79                 BA = xl_fields.BA
  80                 BB = xl_fields.BB
  81                 bt = Signal(2, reset_less=True)
  82                 ba = Signal(2, reset_less=True)
  83                 bb = Signal(2, reset_less=True)
  84 
  85                 # Stupid bit ordering stuff.  Because POWER.
  86                 comb += bt.eq(3-BT[0:2])
  87                 comb += ba.eq(3-BA[0:2])
  88                 comb += bb.eq(3-BB[0:2])

also, there is even some cases where the opcode is further decoded
inside an FU, rather than do it in the CSV files and give it a
special (separate) OP_XXXX

in this way it will be possible to pick up the immediate *without*
needing to go to the lengths (a lot of trouble) of adding a 4th
Operand Decoder.

ah - found it:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/cr/main_stage.py;h=5f1edc7adb6fed02a2fc08b2a5ff0891905eabe9;hb=04c4144f0d962bb181c69de4ce5a998077314e24#l62

  62         # ##### crand, cror, crnor etc. #####
  63         with m.Case(MicrOp.OP_CROP):
  64             # crand/cror and friends get decoded to the same opcode, but
  65             # one of the fields inside the instruction is a 4 bit lookup
  66             # table. This lookup table gets indexed by bits a and b from
  67             # the CR to determine what the resulting bit should be.
  68 
  69             # Grab the lookup table for cr_op type instructions
  70             lut = Signal(4, reset_less=True)
  71             # There's no field, just have to grab it directly from the
insn
  72             comb += lut.eq(op.insn[6:10])

so instead of lut = Signal(4) it would be lut = Signal(8)
and the assignment would either come from self.fields.FormTTI.TTI
or just directly accessing the instruction (bearing in mind
Power ISA spec madness)

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