[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

--- Comment #8 from Jacob Lifshay <programmerjake at gmail.com> ---
maybe we should have:
input A: RA
input B: RB
input C: RT
input D: imm
output: RT

since that way we won't need to shift RA and RB over into inputs B and C saving
a few gates.

input D can just be implicit in the CSV (the ALU extracts the immediate rather
than using the decoder to do that) until we implement 4-in 1-out instructions.

How does that sound?

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