[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hmmm no.  instead of adding extra options (requiring changes to
power_decoder2.py) i noticed that

* In3Sel can select RC
* In2Sel can (as always) select RB
* In1Sel can select RS (for logical ops)

but - drat: this still leaves RT as being only an output.

drat, power_decoder2.py will need a special-case for OP_TERNARY
to select RT as an *input* - 

 | 0.5|6.10|11.15|16.20| 21..25| 26..30   |31|
 | -- | -- | --- | --- | ----- | -------- |--|
 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |Rc|
        ^
        | input into InSel3

for i in range(64):
    idx = RT[i] << 2 | RA[i] << 1 | RB[i]
    RT[i] = (imm & (1<<idx)) != 0

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