[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=741

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
just spotted this:

@@ -475,6 +478,7 @@ class In3Sel(Enum):
     FRS = 3
     FRC = 4
     RC = 5  # for SVP64 bit-reverse LD/ST
+    CONST_TII = 6  # for ternaryi

that won't work.  there are 3 register inputs: all 3 are required
as actual registers

* In1Sel = RA
* In2Sel = RB
* In3Sel = RC

if there was an In4Sel *that* could be set to CONST_TII
(or, better, In2Sel could be set to CONST_TII and In4Sel
allowed to be RC)

however, an In4Sel as explained in comment #5 is a hell of a lot
of work for a lot of pain / pressure (time, resources, regfile
port pressure)

three input registers are required.  the pseudocode is:

for i in range(64):
    idx = RT[i] << 2 | RA[i] << 1 | RB[i]
    RT[i] = (imm & (1<<idx)) != 0

and what that means is: Insel3 needs to have *RT* as an input
option:

@@ -475,6 +478,7 @@ class In3Sel(Enum):
     FRS = 3
     FRC = 4
     RC = 5  # for SVP64 bit-reverse LD/ST
+    RT = 6  # for ternaryi to be able to use RT as an overwrite-input

i'll sort that now.

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