[Libre-soc-bugs] [Bug 741] bitmanip ALU implementation
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Sat Nov 6 11:12:30 GMT 2021
https://bugs.libre-soc.org/show_bug.cgi?id=741
--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok, morning now: can do a more in-depth response / walkthrough / insights
* ternary is an overwrite 4-in 1-out instruction. this is like nothing
that Power ISA has seen before. (overwrite: the destination is also
one of the sources)
* ternaryi is an overwrite 3-in 1-out large-immediate instruction.
other Power ISA 3-in 1-out instructions include FMAC and MAC.
those other Power ISA 3-in/1-out instructions do not include Rc=1
because again it is a mad amount of registers
* ternarycr is an overwrite 3-in 1-out large-immediate instruction
where SVP64 is expected to extend the 3-bit-only fields to 5-bit.
it is reasonably similar to crops (extends the 2-bit selection
to 3-bit). its primary purpose is for manipulating predicates,
hence the 4-bit "mask" option to be able to select one or multiple
of EQ/LT/GT/SO.
the problematic one is ternary. given that no other Function Unit
has 4-input 64-bit pathways it is a lot of work and will be
slow or resource-hungry.
because of the time-pressure i do not recommend it be included:
it will require the addition of a 4th register decoder
(In4Sel), the addition of a 4th input register column in all
CSV files, the addition of
OR
use one single 64-bit input register and split it into 4 parts
(see "swizzle and vec4" variant)
* part 1: input 1
* part 2: input 2
* part 3: input 3
* part 4: 8-bit selector
SVP64 will be capable of dropping down to:
* 64-bit - 16-bit for parts 1-3
* 32-bit - 8-bit for parts 1-3
* 16-bit - 2-bit for parts 1-3
* 8-bit undefined
the advantage of not doing a 4-in 1-out variant is that the
pressure on the opcode space is greatly reduced:
0.5 6.10 11.15 16.20 21.25 26...30 31
NN RT RA RB RC mode 001 Rc
001 would be "freed", potentially for use for svp64 ops
(have to examine that).
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