[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to klehman9 from comment #27)

> So in state, register CR7 would show up in the expect code as expected =
> cr[0].  CR6 is cr[1] etc.

ah... no.  it's more complicated than that: the individual 4-bit CR Fields
are in MSB0 bit order (!)

the numbering we chose CR0-CR7 meets cr[0] and cr[7] etc.

> I can add a comment on the end of those lines making the human reader/tester
> more aware of how they are handled such as # Set CR7 even though it looks
> like assigning something to expected.cr[0].

nope :)

however... when those 8 4-bit CR Fields are placed into the 32-bit CR register,
*THAT* is where you must do the inversion of the numbering!

what will make you totally cry and go bananas is that IBM actually made
the CR register 64-bit

and, because of the MSB0 numbering, the 8 4-bit CR fields do not go into
CR_register[0..31], they go into CR_register[32..63]!!!

as if that wasn't enough, python end-point is inclusive so it's actually
CR_register[32:64]

at this point your brain should have melted or you should be screaming
and/or bashing your head against the nearest spiked metal object in order
to stop the pain, exasperation, and abject horror.

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