[Libre-soc-bugs] [Bug 730] adapt ALU test cases to include expected results

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=730

--- Comment #27 from klehman9 at comcast.net ---
Yeah, solution I'm thinking of for this is to revert my last fix which
basically sets the cr bits properly in expected.  It just copied from a last
state which, while bit order is correct, is reversed from the readable assembly
instruction where the confusion started.

So in state, register CR7 would show up in the expect code as expected = cr[0].
 CR6 is cr[1] etc.

I can add a comment on the end of those lines making the human reader/tester
more aware of how they are handled such as # Set CR7 even though it looks like
assigning something to expected.cr[0].

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