[Libre-soc-bugs] [Bug 739] NGI POINTER Gigabit Router Pinout Considerations

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=739

--- Comment #6 from andrey at technepisteme.xyz ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> https://libre-soc.org/180nm_Oct2020/ls180/
> 
> Andrey notice how the Power is not completely in the corner,
> but is not in the middle either, but also how they group
> together.
Will keep in mind.

> also note, PLL is right in the top corner, and, also, note
Same placement as LS180?

> that any clock lines are (or should) be away from unrelated
> high speed transients.  e.g. ULPI CLK should not be directly
> next to an EINT which might be for an external button with a
> lot of "bounce" on the contacts.
Noted. Should I also consider GPIOs to be potential transient sources as well
(and keep them away from clocks)?


Also, to add a new class/module (for a new chip pinout):
1. Create a .py file for the soc (for example "ngi_router.py"), using one of
the previous chips as a template.
2. Import the new module to src/spec/__init__.py, "from spec import ngi_router"
3. Add a new entry to the modules dict in src/spec/__init__.py, "'ngi_router':
ngi_router"

pinmux_generator.py will now recognise the new chip module. I initially had
issues as I didn't do steps 2 and 3 hahaha

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