[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #10 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #9)
> (In reply to Jacob Lifshay from comment #8)
> > I wrote a superscalar branch predictor that handles next-pc logic, 
> 
> a branch predictor is a non-essential task.  anything that requires any
> kind of cancellation (branch prediction being one such) is completely
> off the table: stall is the sole exclusive option until such time as
> code execution is successful.

we could have the fetch pipe fetch ahead...execution could still always stall
rather than speculating -- all that would happen is it will have fetched the
correct target instead of always obliviously fetching the instructions
immediately following the branch so a branch doesn't always require flushing
the entire fetch pipe... that will speed the whole cpu up by probably 50%.
> 
> there is insufficient time to do otherwise.

it isn't that complex imho... just an idea that we can use (or not).

> > I wrote it as part of an attempt to show that a simple superscalar OoO
> > register-renaming cpu wouldn't take a month to write.
> 
> the focus of this bugreport has nothing to do with OoO or
> register renaming, please keep it focussed exclusively on
> the set task so as not to cause distraction.

yup...just explaining where the code comes from.

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