[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)
> I wrote a superscalar branch predictor that handles next-pc logic, 

a branch predictor is a non-essential task.  anything that requires any
kind of cancellation (branch prediction being one such) is completely
off the table: stall is the sole exclusive option until such time as
code execution is successful.

there is insufficient time to do otherwise.

> it could
> probably be adapted for the in-order cpu by setting the issue width to
> 4-bytes (or 8-bytes if we want to handle any openpower v3.1 instructions).

no, those are off the table, too.

there is insufficient time.

> It has ready/valid inputs/outputs so should be pretty easy to integrate.

doesn't help if there is no InOrder Issuer to integrate into.

please keep this bugreport focussed on getting the required bare
minimum features completed as quickly as possible.

> I wrote it as part of an attempt to show that a simple superscalar OoO
> register-renaming cpu wouldn't take a month to write.

the focus of this bugreport has nothing to do with OoO or
register renaming, please keep it focussed exclusively on
the set task so as not to cause distraction.

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