[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Nov 1 23:37:51 GMT 2021


Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
                 CC|                            |programmerjake at gmail.com

--- Comment #8 from Jacob Lifshay <programmerjake at gmail.com> ---
I wrote a superscalar branch predictor that handles next-pc logic, it could
probably be adapted for the in-order cpu by setting the issue width to 4-bytes
(or 8-bytes if we want to handle any openpower v3.1 instructions). It has
ready/valid inputs/outputs so should be pretty easy to integrate.

BranchPredictor class:


I wrote it as part of an attempt to show that a simple superscalar OoO
register-renaming cpu wouldn't take a month to write.

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