[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

Jacob Lifshay <programmerjake at gmail.com> changed:

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                 CC|                            |programmerjake at gmail.com

--- Comment #8 from Jacob Lifshay <programmerjake at gmail.com> ---
I wrote a superscalar branch predictor that handles next-pc logic, it could
probably be adapted for the in-order cpu by setting the issue width to 4-bytes
(or 8-bytes if we want to handle any openpower v3.1 instructions). It has
ready/valid inputs/outputs so should be pretty easy to integrate.

BranchPredictor class:
https://salsa.debian.org/Kazan-team/reg_rename_demo_cpu/-/blob/9c8690b116b0ad775aaeef066760a29ca6e60979/reg_rename_demo_cpu/fetch.py#L349

tests:
https://salsa.debian.org/Kazan-team/reg_rename_demo_cpu/-/blob/9c8690b116b0ad775aaeef066760a29ca6e60979/reg_rename_demo_cpu/test_fetch.py#L76

I wrote it as part of an attempt to show that a simple superscalar OoO
register-renaming cpu wouldn't take a month to write.

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