[Libre-soc-bugs] [Bug 737] in-order single-issue Power ISA 3.0 core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=737

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #6)
> I think I'd prefer to start from a clean (empty) InOrderIssuer.py, and copy
> things over from TestIssuer.py as needed. Another way would be to make a
> full copy, and try to morph it incrementally, one FSM at a time, while
> making sure the tests still pass. What do you think?

well, the FSMs were not designed for single-clock, they were in most cases
designed for multi-clock operation.  much of the "setup" though (interfaces,
in/out, PowerDecoder2, core, DMI interface) will remain exactly the same
(it has to, really)

honestly, though, because of using the StageAPI, it may be simpler just
to write it from scratch, even starting from not actually having a core
at all but just fetch, issue (ignore it), increment the PC.

really there should not be more than 450 lines of code (even when including
DMI, DEC and TB), so cutting out the core (entirely, pretending the instruction
has been executed with a "fake" ALU, or not even looking at the MultiCompUnit
signals), it should be quite straightforward.

btw i have started on compunits adding ReservationStations, only to find
that the Mux-In and Mux-Out classes are hopeless :)  they do not meet the
ready/valid API properly and i think i know why: the Mux-Out needs a
"busy" flag, per fan-out output.

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