[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/common_output_stage.py;hb=HEAD

cesar, here is where (for ALUs) the zeroing would be hooked in, towards the
end.

when we do SIMD it will be partial zeroing based on 1, 2, 4 or 8 bits of
predicate mask, which will also need to be passed in to the Input Record.

only when all 1 2 4 or 8 predicate mask juts are zero could we skip the entire
operation and directly write zero to thev
 regfile.

this tells us that it is an optimisation to do that.

so, first step, don't worry about optimisation, simply test in the common
output stage, if zeroing and predicate bit is clear, put a zero in the ouutput
instead of the result.

ironically i cannot remember if the CR0 has to be zero'd (or, more to the
point, the CR0 set to ==zero)

-- 
You are receiving this mail because:
You are on the CC list for the bug.