[Libre-soc-bugs] [Bug 491] MMU POWER9 pipeline needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=491

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           See Also|                            |https://bugs.libre-soc.org/
                   |                            |show_bug.cgi?id=604

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
dcache, mmu, and the MMU FSM, are all linked up.  currently debugging, the
wishbone interface is lacking "stall" signalling which is causing issues.

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