[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #27 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #23)
> commit 800e4d580b833f1307bf447987a1bc3acf2515a4 (HEAD -> master)
> Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> Date:   Sat Feb 20 14:30:07 2021 +0000
> 
>     add Wishbone-wrapped SPBlock_512W64B8W
> 
> now this needs adding to ls180.  once added i cannot simulate it (because it
> is
> an Instance),

Maybe you can make the block with an option simulation=(False|True) so you can
have a Wishbone wrapped Memory block during simulation ?

> and i cannot P&R it because there is no Symbolic representation.

As intermediary step, you should be able to do synthesis using for example
nsxlib and then simulate the design post-synthesis using a VHDL or verilog
model for the SRAM block.

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