[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Feb 20 15:32:06 GMT 2021


--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

commit 342a89ebd25fa4c988826d01e1db0ff3d24387a0
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Feb 20 15:25:29 2021 +0000

    add 4k sram build

ok that's in.  

* the QTY 4of SPBlock512W64B8W instances are actually created
  in nmigen using Instance(), exposed via QTY 4of Wishbone Buses

* QTY 4of Wishbone Buses are created by TestIssuer Verilog
  (make ls180_verilog)

* litex libresoc/core.py "picks up" those QTY 4 Wishbone Buses

* litex ls180soc.py actually connects those up onto the main litex
  interconnect bus.

* make ls180 in soc/litex/florent/Makefile constructs the ilang file

it's done this way because there's not a cat in hell's chance i'm going
to modify or add to litex.  i'm sure it's possible: it's just so devoid of
debug-messages and error-catching that it's not worth the risk.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list