[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #26 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=342a89ebd25fa4c988826d01e1db0ff3d24387a0

commit 342a89ebd25fa4c988826d01e1db0ff3d24387a0
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Feb 20 15:25:29 2021 +0000

    add 4k sram build

ok that's in.  

* the QTY 4of SPBlock512W64B8W instances are actually created
  in nmigen using Instance(), exposed via QTY 4of Wishbone Buses

* QTY 4of Wishbone Buses are created by TestIssuer Verilog
  (make ls180_verilog)

* litex libresoc/core.py "picks up" those QTY 4 Wishbone Buses

* litex ls180soc.py actually connects those up onto the main litex
  interconnect bus.

* make ls180 in soc/litex/florent/Makefile constructs the ilang file


it's done this way because there's not a cat in hell's chance i'm going
to modify or add to litex.  i'm sure it's possible: it's just so devoid of
debug-messages and error-catching that it's not worth the risk.

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