[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 0cd474099a8106c81178c6ac1cd507737068d24d (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Feb 20 15:22:18 2021 +0000

    add litex wishbone interconnect to 4x 4k SRAMs
    also had to add one more of the massive DFF 512 byte SRAMs in order to
cover
    all the exception areas (0x900) without going into 4k SRAM area,
    which litex demands to be on an aligned boundary

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