[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #27)

> Maybe you can make the block with an option simulation=(False|True) so you
> can have a Wishbone wrapped Memory block during simulation ?

ah! i think there might be a way to detect "platform=" when running
simulations.

> > and i cannot P&R it because there is no Symbolic representation.
> 
> As intermediary step, you should be able to do synthesis using for example
> nsxlib and then simulate the design post-synthesis using a VHDL or verilog
> model for the SRAM block.

good point.

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