[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Feb 13 22:45:13 GMT 2021


--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #33)
> (In reply to Cesar Strauss from comment #32)
> > It works! Pushed.
> wha-hey!  again, 
> > > do make sure that test_issuer.py still passes (except that annoying bpermd
> > > which is a bug in ISACaller not the hardware)
> > 
> > I does. It also passes test_issuer_svp64.py, which contains a test with a
> > prefix, but with VL=1 for now.
> excellent.  next step is the regfile stepping, but first i'd like to make
> that a module.


see regspec_decode_read() - the Mux() on the isvec, this is too complex to
put into the function.

instead what i will do is augment PowerDecoder2 so that it contains the
Mux, there.

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