[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #33 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #32)

> It works! Pushed.

wha-hey!  again, 

> > do make sure that test_issuer.py still passes (except that annoying bpermd
> > which is a bug in ISACaller not the hardware)
> 
> I does. It also passes test_issuer_svp64.py, which contains a test with a
> prefix, but with VL=1 for now.

excellent.  next step is the regfile stepping, but first i'd like to make
that a module.

> I added a check in check_regs() at test_core.py to also compare the PC with
> the simulated PC. 

i saw that.  also, really, MSR and SVSTATE should be checked here, too.
(all three are part of the State Regfile).

> This is to check that the instruction size was correctly
> taken into account when calculating the next instruction address. Could be
> useful for testing branches as well.

yes, good point.

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