[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=583

--- Comment #32 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #31)
> (In reply to Cesar Strauss from comment #30)
> > The SVP64 prefix fetch and decode is already working locally. I'll just need
> > to test it a little more, add some comments, polish, etc, before pushing.

It works! Pushed.

> do make sure that test_issuer.py still passes (except that annoying bpermd
> which is a bug in ISACaller not the hardware)

I does. It also passes test_issuer_svp64.py, which contains a test with a
prefix, but with VL=1 for now.

I added a check in check_regs() at test_core.py to also compare the PC with the
simulated PC. This is to check that the instruction size was correctly taken
into account when calculating the next instruction address. Could be useful for
testing branches as well.

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