[Libre-soc-bugs] [Bug 583] Implement simple VL for-loop in nMigen for TestIssuer

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun Feb 14 13:04:13 GMT 2021


--- Comment #35 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar i've added SVSTATE to CoreState, plus a read of the State regfile
at the exact point that MSR is done (same technique).

that is now available in PowerDecoder2 (because PowerDecoderSubset
takes a CoreState Record: might have to remove that, make it only
PowerDecoder2, have to see)

*now* i can do that Mux(is_vec, srcstep+read_data1, read_data1)
and in theory that should just "work".

can you do "setup" of SVSTATE? for now, just hack it with a yield
just after setup_memory/setup_regs in test_runner.py
the fields of the test.svstate should be transferred into

(oh btw, see class RegFiles in regfiles.py, you can refer to
 core.regs.rf['state'] as just "core.regs.state")

see in setup_regs()?

    intregs = core.regs.int
    for i in range(32):
        if intregs.unary:
            yield intregs.regs[i].reg.eq(test.regs[i])
            yield intregs.memory._array[i].eq(test.regs[i])

so it can be done as (because state is a RegFileArray)

    stateregs = core.regs.state
    yield stateregs.regs[State.SVSTATE].reg.eq(test.svstate)

something like that.

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