[Libre-soc-bugs] [Bug 753] New: simulator somehow ends up with SO set even though nothing writes to it
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Thu Dec 9 06:12:44 GMT 2021
https://bugs.libre-soc.org/show_bug.cgi?id=753
Bug ID: 753
Summary: simulator somehow ends up with SO set even though
nothing writes to it
Product: Libre-SOC's second ASIC
Version: unspecified
Hardware: PC
OS: Linux
Status: CONFIRMED
Severity: major
Priority: ---
Component: source code
Assignee: lkcl at lkcl.net
Reporter: programmerjake at gmail.com
CC: libre-soc-bugs at lists.libre-soc.org
Blocks: 745
NLnet milestone: ---
running src/soc/fu/shift_rot/test/test_pipe_caller.py
at soc.git:
commit 031bebcc32d72f2000f13a316dae1f1cb4a8874d (HEAD -> master, origin/master,
origin/HEAD)
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Wed Dec 8 22:05:15 2021 -0800
add bitmanip tests
openpower-isa.git:
commit 950e54f10be461122e30fde1b2957b342bb9b0ba (HEAD -> master, origin/master,
origin/HEAD)
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Wed Dec 8 22:04:10 2021 -0800
make ternlogi tests run
Traceback (most recent call last):
File "src/soc/fu/shift_rot/test/test_pipe_caller.py", line 157, in process
yield from self.execute(alu, instruction, pdecode2, test)
File "src/soc/fu/shift_rot/test/test_pipe_caller.py", line 126, in execute
yield from self.check_alu_outputs(alu, pdecode2,
File "src/soc/fu/shift_rot/test/test_pipe_caller.py", line 188, in
check_alu_outputs
ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
File ".../openpower-isa/src/openpower/test/common.py", line 581, in
check_cr_a
dut.assertEqual(cr_expected, cr_actual, msg)
AssertionError: 9 != 8 : CR0 .4byte 0x14642ff9 # ternlogi. 3, 4, 5, 255
Referenced Bugs:
https://bugs.libre-soc.org/show_bug.cgi?id=745
[Bug 745] OP_TERNARY instruction
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