[Libre-soc-bugs] [Bug 753] simulator somehow ends up with SO set even though nothing writes to it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=753

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
  1 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry
in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl
pipe,comment,form,CONDITIONS,unofficial,comment2
   2
--------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternlogi,TLI,,1,unofficial
until submitted and approved/renumbered by the opf isa wg

"RC=1" is a request to PowerDecoder2 to decode both OE and Rc flags,
which will then (sigh) decode those bits manually (a hangover from
using microwatt decode1.vhdl and decode2.vhdl)

try this:

   0,0,RC,0
   ==>
   0,0,NONE,0

this tends to suggest that disallowing Rc=1 for ternlog is probably a good
idea [and would free up more bits]

   A,RB,RT,RT,NONE,CR0,0,0,ZERO
   ==>
   A,RB,RT,RT,NONE,NONE,0,0,ZERO

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