[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #20)

> 1236 for i in range(NUM_WAYS):
> 1237     with m.If(i == replace_way):
> 1238         ts = Signal(INDEX_BITS)

wrong width.

> 1239         comb += ts.eq(cache_tags[r.store_index])
> 1240         comb += ts.bit_select(i, TAG_BITS).eq(

word_srlect.

> 1241                  r.store_tag
> 1242                 )
> 1243         comb += tagset.eq(ts)
> 1244         sync += cache_tags[r.store_index].eq(tagset)
> ```
> 
> The code for write_tag for quick reference:
> ```
> def write_tag(way, tagset, tag):
>     return tagset[way * TAG_BITS:(way + 1) * TAG_BITS].eq(tag)
> ```

oh, errr then forget that for now write_tag actually looks reasonable.

leave it for now

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