[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #21 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Jacob Lifshay from comment #18)

> eq(<Python int>) sets the bits to the sign-extended version if the int is
> negative and to the zero-extended version otherwise. It always sets all bits
> of the thing eq() is called on.

Hmmm...

(In reply to Luke Kenneth Casson Leighton from comment #19)
> (In reply to Cole Poirier from comment #15)
> 
> > !! So eq(1) is only the first bit, but eq(0) is all the bits of the Signal?
> 
> incorrect. 
> 
> whatever value you place into the LHS is zero extended.
> 
> therefore eq(1) will be 1 in the LSB and all zeros in the remaining MSBs.
> 
> which is why eq(~1) is especially doubly wrong.
> 
> this places 0b1111111111111111111110 into the LHS i.e a 0 in the LSB and all
> 1s in the MSBs.

Aha! Ok understood now... mostly... I think.

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