[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
1243 #               -- Requests are all sent if stb is 0
1244 #               stbs_done := r.wb.stb = '0';
1245                 # Requests are all sent if stb is 0
1246                 sync += stbs_done.eq(r.wb.stb == 0)

likewise stbs_done will here be set ONLY ON THE NEXT CYCLE yet the expectation
is clearly for use in this FSM state.

you want comb += just like i did in dcache.

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