[Libre-soc-bugs] [Bug 485] Create I-Cache from microwatt icache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=485

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
1227 #                   if i = replace_way then
1228 #                       tagset := cache_tags(r.store_index);
1229 #                       write_tag(i, tagset, r.store_tag);
1230 #                       cache_tags(r.store_index) <= tagset;
1231 #                   end if;
1232 #               end loop;
1233                     for i in range(NUM_WAYS):
1234                         with m.If(i == replace_way):
1235                             sync += tagset.eq(cache_tags[r.store_index])
1236                             sync += write_tag(i, tagset, r.store_tag)
1237                             sync += cache_tags[r.store_index].eq(tagset)

on clock cycle N+1, tagset gets updated.
on clock cycle N, write_tags gets updated but using the value of tagset from
cycle N-1 because of the sync on tagset.

you have to keep in mind that all output from sync will ONLY change on the NEXT
cycle.

you want comb += tagset.eq(....)

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