[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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         Depends on|                            |493

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #3)

> For pure nmigen code maybe the JTAG simulation infrastructure could be ported
> from cocotb to pysim/cxxsim. But I guess due to the use of litex the

i have a *very* basic unit test now with DMI2JTAG operational and reading
IDCODE

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/dmi2jtag.py;h=119aaf9860ff0f52e93f8fd2945cd7333c1a9962;hb=fd902da6f694e68a4c664786fd02857866d90d3e#l239

staf looking at the VCD files it seems that the addresses are stored in
reverse-bit-order which is quite interesting but has no impact on functionality

i may add one more unit test (JTAG wishbone read/write) and then i am going
to add this to ls180.

staf it would be nice to have DMI2TAG added to c4m jtag tap.py


Referenced Bugs:

https://bugs.libre-soc.org/show_bug.cgi?id=493
[Bug 493] DMI JTAG SERDES needed, to be translated from
microwatt/dmi_dtm_xilinx.vhdl
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