[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
      New connections: $memory\mem$rdmux[0][7][48]$b$89345 [13] =
$memory\mem$rdmux[0][7][48]$b$89345 [11]
    Consolidated identical input bits for $mux cell
$memory\mem$rdmux[0][8][98]$89877:
      Old ports: A=$memory\mem$rdmux[0][8][98]$a$89878,
B=$memory\mem$rdmux[0][8][98]$b$89879, Y=$memory\mem$rdmux[0][7][49]$a$89347
      New ports: A={ $memory\mem$rdmux[0][8][98]$a$89878 [31:26]
$memory\mem$rdmux[0][8][98]$a$89878 [24:21] $memory\mem$rdmux[0][8][98]$a$89878

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