[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #3)

> For pure nmigen code maybe the JTAG simulation infrastructure could be ported
> from cocotb to pysim/cxxsim. But I guess due to the use of litex the
> libre-SOC
> won't be a pure nmigen design either.

no, however i can at least do a basic unit test in nmigen, checking that
JTAG creates WB requests correctly.

> 
> Nice thing is that the tested .svf files in simulation could also be used
> later to test the chips. For Retro-uC I actually did both test .svf file in
> cocotb and later on FPGA using openOCD to play the .svf file.

i like it!  i would really like to work out how to use coriolis2 simulation
of the netlist / transistors, at some point.

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