[Libre-soc-bugs] [Bug 490] Complete peripheral set including litex for first functional POWER9 Core

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=490

Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
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                 CC|                            |staf at fibraservi.eu

--- Comment #3 from Staf Verhaegen <staf at fibraservi.eu> ---
Current way of testing for JTAG implemented in Chips4Makers JTAG is use of
cocotb and .svf files.
.svf files are standardized text format for running tests through JTAG. In the
Chips4Makers repo is a cocotb infrastructure for playing back these .svf files
in a RTL simulation. I used cocotb as in the Retro-uC some nmigen modules are
used which are wrapper around VHDL and Verilog code and pysim can't handle
those.
In theory now cxxsim should be able to handle anything yosys can synthesize.

For pure nmigen code maybe the JTAG simulation infrastructure could be ported
from cocotb to pysim/cxxsim. But I guess due to the use of litex the libre-SOC
won't be a pure nmigen design either.

Nice thing is that the tested .svf files in simulation could also be used later
to test the chips. For Retro-uC I actually did both test .svf file in cocotb
and later on FPGA using openOCD to play the .svf file.

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