[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #28 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #27)
> right, i've gone over dcache.py about 5 times now, just added a set of calls
> to string everything together, added cache_ram.py, last one is plru.py and
> then actually instantiating the module can be done and syntax errors tracked
> down.

Cool! Thanks for all of your help, I'm learning an amazing amount in quite a
short time due to that :)

> for all of this, cole, i'm considering dropping in quite a big bit of the
> MMU budget, around the EUR 1600 mark, 50:50 because it's a heck of a lot of
> work.

Sounds reasonable to me, the translation from vhdl was the easy part, linking
it up properly and testing it should be quite the fun process ;)

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