[Libre-soc-bugs] [Bug 407] XICS interrupt controller is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=407

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit 2a187089be6e063f6bcaf8c27bfe82a5fe76570c
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Sep 5 14:38:08 2020 +0100

    add simple GPIO peripheral to verilog TestIssuer


commit 63ccd4c6351103b904a956b7963cf42f53e748ca (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sat Sep 5 15:03:21 2020 +0100

    add simple GPIO wishbone bus to litex sim.py

-- 
You are receiving this mail because:
You are on the CC list for the bug.