[Libre-soc-bugs] [Bug 407] XICS interrupt controller is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=407

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
commit ffe70742b1fb287ba1766df8a8e55ec2190db797 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Fri Sep 4 16:11:10 2020 +0100

    adding option to include XICS external interrupts.
    XICS ICP and ICS are included, the wishbone slave ports added to TestIssuer
    then if ext_irq is raised in core, execution jumps to 0x500 through a TRAP


commit 39f8d6aa73fd74610eeb354f76532fa2413ba2a4 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Fri Sep 4 16:16:40 2020 +0100

    bring out XICS ICS interrupt levels so that they can be wired to
peripherals

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