[Libre-soc-bugs] [Bug 352] virtual (dependency-tracked) regfile (cache) needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=352

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
so imagine a matrix, ISAregs on the rows, virtual regs on the columns.

on each ISAreg at the left is a bitfield which is our "active renamers" that
also if 0b0000 tells us that the ISAreg is not in use.

along the top is another bitfield vector telling us which virtual regs are in
use

in every cell is a Latch which says whether redirection from ISAreg A is active
to Virtual reg B.

then, for each "issue" (1, 2, 3, 4) in multi-issue are required independent
column *and* row activation wires that will allow the Latch to be set.  if
there is to be 4-multi issue, 4 sets of independent row-column grid wires are
needed.

then (and the above grid wires can probably be shared with this), a way to pass
through information about the regfile ports is needed, this being the whole
purpose, that the virtual regs gets redirected to real ones.

giving each regfile port a binary ID (read and write) the ID can be passed up
from the bottom, along with a request, "please redirect to real".

on reaching the cell with the active latch the entire ID on that column is
passed to the *row* wires using simple AND and OR gates.

the ID is received by the regfile to tell it which port to activate.

the data will then be read/written on the appropriate numbered regfile
broadcast bus.

deactivation is cleared by column, matching the FUREGs reset, and because there
is only one latch ever set per column (and row) a grid reset is not needed,
just column wires.

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