[Libre-soc-bugs] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #65 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> basically, we need:
> 
> * one function (similar to TestInput.send) which takes care of *one*
>   REQ_READ and GO_RD signalling bit.  it should monitor:
>   self.rd.req[N], then set self.rd.go[N] for *one* cycle (one blank yield)
>   then set it self.rd.go[N] back to zero and confirm (assert) that
>   self.rd.req[N] has gone to zero

commit ff916d3932fc4fe90c9e8d1cc3bfa8c3818dceb9
Author: Cesar Strauss <cestrauss at gmail.com>
Date:   Wed Oct 28 19:57:55 2020 -0300

    Implement an operand producer that talks the rel_o/go_i handshake

    It can be instantiated once for each operand port, working in parallel
    with the main test-bench process.

https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=ff916d3932fc4fe90c9e8d1cc3bfa8c3818dceb9

> * another function (similar again to TestInput.rcv) which does the same
>   thing for REQ_WRITE and GO_WRITE.
> 
> * another function - a very simple one - which sets issue_i
>   for one cycle (yield in between), then waits for "self.busy" to drop to 0
> 
> we can make it more sophisticated as we go along.
> 
> it should be... only... about... 80 lines of code, at a guess.

This will be next.

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