[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #31)
> (In reply to Luke Kenneth Casson Leighton from comment #30)
> > (In reply to Cole Poirier from comment #29)
> > > ```proposed FPGA External Pin to STLINK JTAG pin connecitons
> > >     pin #  | label # | FPGA IO PAD | GPIO # (n/p) | JTAG Pin # (Signal)  |
> > >  1         |  3.3v   |    NONE     |     3v3      |      1 (MCU VDD)     |
> > >  2         |  3.3v   |    NONE     |     3v3      |      2 (MCU VDD)     |
> > 
> > good, yes.  the power *from* the ulx3s goes *into* the IO side of the
> > STLinkv2
> > so as to provide the Reference Voltage it needs relative to ulx3s's IO.
> 
> Understood.
> 
> 
> > >  3         | -|(GND) |    NONE     |     GND      |      3 (JNTRST)      |
> > 
> > don't connect up reset, it's a driving pin (output) and it looks like you
> > shorted it to GND.  that would damage the STLinkv2.
> 
> Ok. I would not have been able to figure that out on my own. Where can I
> learn these fundamental principles of electronics?

a search "short circuit" gives a good explanation
https://en.m.wikipedia.org/wiki/Short_circuit

in this case, one of the voltages is "GND" and the other would have been
"JNTRST".

> Can you review the new proposed connection plan?

if it is no different other than removing the RST signal it looks good.

btw again, reminder to trim context in replies.

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